COMPLEMENTARY OUTPUTS AND EDGE TRIGGERED AND HERMETICALLY SEALED AND HIGH SPEED AND MONOLITHIC AND POSITIVE OUTPUTS AND PRESETTABLE AND W/CLEAR AND W/ENABLE
CQSJ
INCLOSURE MATERIAL
CERAMIC AND GLASS
CQSZ
INCLOSURE CONFIGURATION
DUAL-IN-LINE
CQWX
OUTPUT LOGIC FORM
TRANSISTOR-TRANSISTOR LOGIC
CQZP
INPUT CIRCUIT PATTERN
DUAL 4 INPUT
CSSL
DESIGN FUNCTION AND QUANTITY
2 FLIP-FLOP,D-TYPE
CTFT
CASE OUTLINE SOURCE AND DESIGNATOR
T0-116 JOINT ELECTRON DEVICE ENGINEERING COUNCIL
CZEQ
TIME RATING PER CHACTERISTIC
50.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME,LOW TO HIGH LEVEL OUTPUT AND 50.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME,HIGH TO LOW LEVEL OUTPUT
TEST
TEST DATA DOCUMENT
80063-SM-B-641496 DRAWING (THIS IS THE BASIC GOVERNING DRAWING,SUCH AS A CONTRACTOR DRAWING,ORIGINAL EQUIPMENT MANUFACTURER DRAWING,ETC.; EXCLUDES ANY SPECIFICATION,STANDARD OR OTHER DOCUMENT THAT MAY BE REFERENCED IN A BASIC GOVERNING
Components Related to NSN - 5962-00-247-3396, 5962002473396
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